1. Field of the Invention
The present invention relates to a wiring technique around a semiconductor chip, particularly to a wiring design of a laminated semiconductor package as a semiconductor device having a multi-layered structure constituted by laminating a plurality of semiconductor chips in a plurality of layers.
2. Description of the Related Art
Examples of a semiconductor device include a laminated semiconductor package including a structure obtained by laminating a plurality of layers of semiconductor chips as shown in FIG. 17, that is, a so-called multi-chip package 101. The package 101 is constituted by laminating a plurality of memory chips 105 as the semiconductor chips, in four layers.
An outline of one example of a manufacturing process of the package 101 will be concretely described. First, the chips 105 are mounted one by one onto a plurality of chip-mounting substrates 104, for example, by a flip chip method. Subsequently, a plurality of chip-mounting substrates 104 with the chips 105 mounted thereon are laminated on one intermediate substrate 103 to constitute one system block 102. Subsequently, four blocks 102 are laminated in four layers and packaged to form one module. Thereby, the desired package 101 is obtained.
In general, each chip-mounting substrate 104 includes a chip connecting wiring (not shown) for electrically connecting a chip connecting via terminal (not shown) formed through a thickness direction to a pad (not shown) of the chip 105. Moreover, a via terminal and wiring (not shown) of the same pattern are formed on the intermediate substrate 103. Thereby, the respective chips 105 mounted on the chip-mounting substrate 104 are arranged as one unit for each block 102 and incorporated in the module.
Here, a data amount which can be individually stored for each block 102 is increased in order to increase the data amount which can be stored in the whole package 101. In this case, it is necessary to draw out a plurality of data pins (not shown) of the chip 105 to an external connection terminal (not shown) individually for each block 102. For this, a wiring pattern of a chip connecting wiring has to be formed separately for each layer of the chip-mounting substrate 104.
The wiring pattern for each layer will be briefly described with reference to FIGS. 18 to 21. Data pins 106 of the chip 105 are electrically connected to first to fourth chip connecting via terminals 107a to 107d formed on each of chip-mounting substrates 104a to 104d, and first to fourth interlayer connecting via terminals 108a to 108d formed on each of intermediate substrates 103a to 103d via the wiring pattern. FIGS. 18 to 21 schematically show constitutions of blocks 102a to 102d of first to fourth layers. Moreover, in FIGS. 18 to 21, inner two-dot chain lines show the chip-mounting substrates 104a to 104d of the first to fourth layers, and outer two-dot chain lines show the intermediate substrates 103a to 103d of the first to fourth layers.
On each of the chip-mounting substrates 104a to 104d, the first to fourth chip connecting via terminals 107a to 107d selectively and electrically connected to each of the data pins 106 of the chip 105 are provided at predetermined positions with respect to a mounted position of the chip 105. Similarly, on each of the intermediate substrates 103a to 103d, the first to fourth interlayer connecting via terminals 108a to 108d selectively and electrically connected to each of the data pins 106 of the chip 105 are provided at predetermined positions. The first to fourth interlayer connecting via terminals 108a to 108d are electrically connected to the first to fourth chip connecting via terminals 107a to 107d with a one-to-one correspondence.
Concretely, the first to fourth interlayer connecting via terminals 108a to 108d are continuously connected to the first to fourth chip connecting via terminals 107a to 107d along laminate directions of the blocks 102a to 102d, respectively. Thereby, the interlayer connecting via terminals 108a to 108d are individually and electrically connected to the data pins 106 via the chip connecting via terminals 107a to 107d. Additionally, in FIGS. 18 to 21, the chip connecting via terminals 107a to 107d are shown intentionally deviating from the interlayer connecting via terminals 108a to 108d so that wiring states therebetween can be easily understood. Additionally, in FIGS. 18 to 21, the electric connections between the chip connecting via terminals 107a to 107d and the interlayer connecting via terminals 108a to 108d is shown by a broken line.
Moreover, in actual fact, four chip-connecting via terminals 107a to 107d, and four interlayer-connecting via terminals 108a to 108d are provided for each of all the data pins 106 of the memory chip 105 of each layer. However, in order to understand the wiring state, description of the electric connection state of the chip connecting via terminals 107a to 107d and interlayer connecting via terminals 108a to 108d with respect to one data pin 106 is sufficient. Therefore, only four chip connecting via terminals 107a to 107d, and only four interlayer connecting via terminals 108a to 108d are shown, and the other terminals are omitted.
As described above, it is necessary to independently draw out the data pin 106 of the chip 105 to the external terminal. However, all the via terminals and wirings of the intermediate substrates 103a to 103d are formed in the same pattern. Therefore, for the data pin 106 of the chip 105 of each layer, for example, a data pin 106a via which data managed with the same address is inputted/outputted needs to be electrically connected to the chip connecting via terminals 107a to 107d which differ with each layer.
Therefore, as shown by a solid line in FIG. 18, a first chip connecting wiring 109a is formed on the first chip-mounting substrate 104a so that the data pin 106a is electrically connected to the first chip connecting via terminal 107a. Moreover, as shown by a solid line in FIG. 19, a second chip connecting wiring 109b is formed on the second chip-mounting substrate 104b so that the data pin 106a is electrically connected to the second chip connecting via terminal 107b. Furthermore, as shown by a solid line in FIG. 20, a third chip connecting wiring 109c is formed on the third chip-mounting substrate 104c so that the data pin 106a is electrically connected to the third chip connecting via terminal 107c. Additionally, as shown by a solid line in FIG. 21, a fourth chip connecting wiring 109d is formed on the fourth chip-mounting substrate 104d so that the data pin 106a is electrically connected to the fourth chip connecting via terminal 107d. In this manner, in the package 101, the first to fourth chip connecting wirings 109a to 109d are formed in predetermined wiring patterns which differ with each layer. This can increase the data amount stored in the whole package 101.
For example, in FIG. 17, every 200 substrates of the first to fourth chip-mounting substrates 104a to 104d each having one chip 105 mounted thereon are provided for the first to fourth intermediate substrates 103a to 103d to constitute the package 101. In this case, in an assembling process of the package 101, the respective chip-mounting substrates 104a to 104d each including 200 substrates need to be managed individually for the respective layers so that the substrates are prevented from being mixed among the layers. Moreover, to manufacture one package 101, the chip-mounting substrates 104a to 104d need to be classified for each layer and mounted on the intermediate substrates 103a to 103d so that the chip-mounting substrates 104a to 104d are disposed at predetermined layers, respectively.
Among 800 chip-mounting substrates 104a to 104d in total, for example, if only each one substrate for arbitrary two layers, that is, two substrates in total of the chip-mounting substrates 104a to 104d are mounted by mistake, the package 101 does not normally operate, and becomes defective. Therefore, there is a possibility that the package 101 has a remarkably low yield. It is remarkably difficult in an actual manufacturing line of the package 101 to manage all of the packages 101 manufactured in mass so that only two of a large number of chip-mounting substrates 104a to 104d are prevented from being mounted by mistake during a mounting operation. When a management system and workers are arranged in order to prevent such mistake, equipment and labor costs increase, a manufacturing cost thereby rises remarkably, and a unit price per unit of the package 101 increases. This remarkably becomes disadvantageous in price competition in a recent semiconductor industry. Moreover, since the manufacturing process of the package 101 easily becomes complicated in such a production system, it is difficult to improve a production efficiency of the package 101.